SOI field effect transistor and corresponding field effect transistor

ABSTRACT

A first SOI field effect transistor with predetermined transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an undoped substrate; a spacer layer having a predetermined thickness on at least a portion of the sidewalls of the laterally delimited layer sequence; and two source/drain regions in two surface regions of the substrate which are adjoined by the spacer layer, with a predetermined dopant concentration profile, the layer sequence and the spacer layer forming a shading structure that prevents dopant from being introduced into a surface region of the substrate between the two source/drain regions during the production of the first SOI field effect transistor, wherein the predetermined transistor properties of the first SOI field effect transistor are set by setting the thickness of the spacer layer and by the dopant concentration profile.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.10/948,637, filed Sep. 23, 2004, which is a continuation ofInternational Patent Application Serial No. PCT/DE03/00933, filed Mar.20, 2003, which published in German on Oct. 2, 2003 as WO 03/081675, theentirety of which are included herein by reference.

FIELD OF THE INVENTION

The invention relates to a method for producing an SOI field effecttransistor and to an SOI field effect transistor.

BACKGROUND OF THE INVENTION

Field effect transistors are required for many applications in siliconmicroelectronics.

In circuit technology, it is often desirable, in modern CMOS processes,to have a plurality of different n-MOS transistors and a plurality ofdifferent p-MOS transistors having different threshold voltages(so-called multi-V_(T) technology, where V_(T) denotes the thresholdvoltage of the transistor). For specific applications, it may benecessary to have transistors with a particularly high switching speed,whereas a minimal leakage current of the transistor is sought in otherapplications. If the multi-V_(T) technology is combined with the use ofdifferent supply voltages V_(DD)of an integrated circuit(multi-V_(DD)/V_(T) technology), then the optimum voltage swing may beselected, depending on the switching activity of a specific transistorof an integrated circuit, in order to achieve maximum boosting of thegate voltage V_(DD)-V_(T). Examples of transistors having suchrequirements are transistors in clock circuits with high switchingactivity, a low voltage swing and a low threshold voltage. In the caseof a transistor in a clock circuit, the leakage current is of relativelylittle relevance on account of the high activity, whereas minimizing thedynamic power loss (which is a function of the square of the supplyvoltage V_(DD)) is of primary interest. By contrast, in logic circuitswith relatively low activity (for example less than 30%), the staticpower loss on account of electrical leakage currents in the switched-offstate is of greater relevance, so that transistors having a higherthreshold voltage are advantageous here. In order not to impair theswitching speed in the active state (the switching-time t_(D) isproportional to 1/[V_(DD)-V_(T)]) and in order to avoid an undesirablereduction of the boosting of the gate voltage, the supply voltageV_(DD)of the logic block is increased correspondingly.

An overview of the multi-V_(DD)/V_(T) circuit technology, in particularwith regard to conventional CMOS technology, is found for example inHamada, M, Ootaguro, Y, Kuroda, T (2001) “Utilizing Surplus Timing forPower Reduction”, Proceedings of the IEEE Custom Integrated CircuitsConference 2001.

A central problem of conventional integrated circuits is the increasingdeterioration of the electrical properties of MOS transistors (“metaloxide semiconductor”) with increasing structural fineness, that is tosay miniaturization. This is caused for example by the punch-througheffect, the latch-up effect and also the parasitic capacitance betweenthe drain/source region and the substrate, the parasitic capacitancegreatly increasing more than proportionally in relation to thetransistor size. The term punch-through effect refers to an undesirablepunch-through of current between adjacent transistors of a transistorarrangement. The term latch-up effect designates the phenomenon whereina transistor of the p conduction type and a transistor of the nconduction type, when the distance between them falls below a minimumdistance, may form a parasitic thyristor at which a high triggeringcurrent may flow, which may effect a local destruction of an integratedsemiconductor component.

The problems described are alleviated in the case of SOI technology(“silicon-on-insulator”) , which uses a silicon layer on a silicon oxidelayer on a silicon substrate as basic material for forming an integratedcircuit. The problems described can be alleviated particularly with theuse of a thin layer of silicon (e.g. having a thickness of 20 nm) on anelectrically insulating silicon oxide layer.

Furthermore, using a doped substrate may give rise to the problem thattechnologically dictated local fluctuations in the dopant concentrationsgive rise to a variation of the threshold voltage in differenttransistors of an integrated circuit. This problem is avoided when anundoped substrate is used.

However, if a thin undoped silicon layer is used as a base layer forforming a field effect transistor, then it is not possible to alter thethreshold voltage of the field effect transistor by setting the dopingof the channel region. In this case, the threshold voltage of a fieldeffect transistor may be defined by defining the work function of thematerial of the gate region. In this case, a separate gate material isin each case required for each type of transistor (low-power transistoror high-performance transistor, p-MOS transistor or n-MOS transistor),the threshold voltage of the respective transistor being defined byselection of the gate material.

However, the free material selection of the gate regions of differenttransistors of an integrated circuit may be restricted for technologicalreasons. Furthermore, it is complicated and therefore expensive to usedifferent gate materials in a method for producing an integrated circuitwith different transistors.

Thin-film SOI transistors (“silicon-on-insulator”) are of interestparticularly in the case of a CMOS technology with dimensions below 50nm. As discussed for example in Schiml, T, Biesemans, S, Brase, G,Burrell, L, Cowley, A, Chen, K C, Ehrenwall, A, Ehrenwall, B, Felsner,P, Gill, J, Grellner, F, Guarin, F, Han, L K, Hoinkis, M, Hsiung, E,Kaltalioglu, E, Kim, P, Knoblinger, G, Kulkarni, S, Leslie, A, Mono, T,Schafbauer, T, Schroeder, P, Schruefer, K, Spooner, T, Towler, F,Warner, D, Wang, C, Wong, R, Demm, E, Leung, P, Stetter, M, Wann, C,Chen, J K, Crabbe, E (2001) “A 0.13 μm CMOS Platform with Cu/Low-kInterconnects for System On Chip Applications” 2001 Symposium on VLSITechnology, Digest of Technical Papers, in view of the high diversity ofcomponents, a plurality of different types of transistor are requiredfor the logic in existing processes of the 130 nm technology. In thecase of three different types of transistor with different thresholdvoltages (high threshold voltage, medium threshold voltage, lowthreshold voltage) and also in the case of two different types of chargecarrier (n-MOS transistor, p-MOS transistor) a total of six differentmaterials result for the gate region. An associated thin-film SOI-CMOSprocess therefore requires a very high process complexity.

In present-day CMOS technologies, the threshold voltage of the fieldeffect transistors used therein is generally set by doping the channelregion. Such implantations include forming LDD regions (“Lightly DopedDrain”), carrying out a pocket doping (localized doping of the regionbetween the source/drain regions or in the channel region, therebyreducing the sensitivity of the transistor to technologically dictatedfluctuations in the length of the gate region), and also forming aretrograde well (clearly a highly doped region within the substratebetween the source/drain regions). However, these implantations aresubject to technologically dictated fluctuations, which result inundesirable fluctuations of the transistor properties. Furthermore,particularly in the case of fully depleted thin-film SOI transistorsprimarily in the case of technology nodes with feature dimensions ofless than 50 nm, it is no longer possible to employ this method forsetting the threshold voltage since the doping-dependent contribution tothe threshold voltage V_(T) ^(dop) is proportional to q*N_(A)*t_(si). Inthis case, t_(si) designates the thickness of the silicon layer, N_(A)designates the dopant concentration in the channel region, and qdesignates the electrical elementary charge. For t_(si)<20 nm andN_(A)<10¹⁶ cm⁻³, V_(T) ^(dop) then has hardly any influence on thethreshold voltage.

The alternative to setting the threshold voltage by means of targeteddoping consists in using a plurality of different gate materials fortransistors with different threshold voltages and also differentconduction types. However, thin-film SOI-CMOS processes that permit theformation of MOS transistors with different threshold voltages do notexist at the present time.

One possibility for setting the transistor properties in SOI technologyis the use of transistors having different lengths of the gate region,since the length of the gate region also has a crucial influence on thethreshold voltage of a field effect transistor. A capability forsufficiently exact setting of the threshold voltage of transistors bysetting the length of the gate region presupposes a sufficiently goodresolution of a masking technique.

FIG. 1A shows an SOI field effect transistor 100 in a technology with aminimum feature dimension that can be achieved of F=150 nm. The SOItransistor 100 has a silicon substrate 101, a silicon dioxide layer 102arranged on the silicon substrate 101, and an undoped silicon layer 103arranged on the silicon dioxide layer 102. The layers 101 to 103 form anSOI layer. A first source/drain region 106 is implanted in a firstsurface region of the undoped silicon layer 103, and a secondsource/drain region 107 is implanted in a second surface region of theundoped silicon layer 103. A region between the two source/drain regions106, 107 of the undoped silicon layer 103 forms the channel region 108.In FIG. 1A, the lateral extent of the gate region 104 is determined bythe smallest feature dimension that can be achieved in the technologygeneration, F=150 nm. A typical value for the inaccuracy duringpatterning is designated by ΔF in FIG. 1A. An accuracy of approximatelyΔF=±20 nm can be achieved with the best patterning methods existing atthe present time (electron beam lithography).

FIG. 1B shows a field effect transistor 110 of a technology generationin which the minimum feature dimension that can be achieved is F=50 nm.Assuming that the best resolution achieved at the present time is ΔF=20nm, then it can be discerned that with conventional masking techniques,when striving for technology generations of 50 nm or less theuncertainties in the accuracy of the mask are too large to set thelength of the gate region or the length of the channel region withsufficient accuracy. The relative accuracy when setting the length ofthe gate region in a technology generation where F=50 nm and with anuncertainty of ΔF=20 nm is 40%.

Therefore, as feature dimensions decrease further, with conventionalmasking technology, the threshold voltage of a transistor cannot be setwith satisfactory accuracy by setting the length of the gate region.Moreover, the costs are very high when using masks. Furthermore, theproduction time of transistors increases more and more as masks becomefiner.

U.S. Pat. No. 5,532,175 discloses a method for adjusting a thresholdvoltage for a semiconductor device on an SOI substrate, in which athreshold voltage adjusting implantation is carried out.

Nuernbergk, D M et al. (1999) “Mache mögen's heiβ—Silicon on InsulatorBauelemente und ihre Besonderheiten”, in: “Mikroelektronik undFertigung”, pages 61 to 64, discloses an overview ofsilicon-on-insulator components and their particular properties.

DE 198 23 212 A1 discloses a semiconductor device in which afield-shielding gate oxide layer is thicker at an edge section of afield-shielding gate electrode below a sidewall oxide layer.

DE 198 57 059 A1 discloses an SOI component and a method for producingit, in which the effect of a body at floating potential is reduced.

U.S. Pat. No. 5,273,915 discloses a method for producing bipolarjunctions and MOS transistors on SOI.

SUMMARY OF THE INVENTION

The invention is based on the problem of providing a possibility foradjusting a transistor property of an SOI field effect transistor withsufficient accuracy and with a tenable outlay.

The problem is solved by means of a method for producing an SOI fieldeffect transistor with predeterminable transistor properties and bymeans of an SOI field effect transistor with predeterminable transistorproperties having the features in accordance with the independent patentclaims.

In accordance with the method according to the invention for producingan SOI field effect transistor with predeterminable transistorproperties, a laterally delimited layer sequence with a gate-insulatinglayer and a gate region is formed on a substrate. Furthermore, a spacerlayer having a predetermined thickness is formed at least on a part ofthe sidewalls of the laterally delimited layer sequence. Moreover, twosource/drain regions having a predetermined dopant concentration profileare formed by introducing dopant into two surface regions of thesubstrate which are adjoined by the spacer layer, the layer sequence andthe spacer layer being set up in such a way that they form a shadowingstructure for preventing dopant from being introduced into a surfaceregion of the substrate between the two source/drain regions. Thetransistor properties of the SOI field effect transistor are set bysetting the thickness of the spacer layer and by setting the dopantconcentration profile.

The SOI field effect transistor according to the invention withpredeterminable transistor properties has a laterally delimited layersequence with a gate-insulating layer and a gate region on a substrate.Furthermore, the SOI field effect transistor has a spacer layer having apredeterminable thickness on at least a part of the sidewalls of thelaterally delimited layer sequence, and also two source/drain regions intwo surface regions of the substrate which are adjoined by the spacerlayer, with a predeterminable dopant concentration profile. The layersequence and the spacer layer are set up in such a way that they form ashadowing structure for preventing dopant from being introduced in asurface region of the substrate between the two source/drain regionsduring the production of the SOI field effect transistor. The transistorproperties of the SOI field effect transistor are set by setting thethickness of the spacer layer and by setting the dopant concentrationprofile.

One basic idea of the invention consists in predetermining a transistorproperty (e.g. the threshold voltage) of an SOI field effect transistorby setting the thickness of a sidewall spacer layer and by adjusting thedopant concentration profile of the source/drain regions. The inventionmakes it possible to define the length of the gate region by means of adeposition method with an accuracy in the angstrom range. Problems knownfrom the prior art (e.g. fluctuations in the dopant concentration in thesubstrate, complicated use of a multiplicity of different gatematerials, etc.) are avoided.

The invention makes it possible to form a circuit arrangement on an SOIsubstrate in which it is possible to form different transistors withdifferent transistor properties (e.g. different threshold voltages forhigh-performance or low-power applications) by applying a spacer layeron a laterally delimited layer sequence comprising gate region andgate-insulating layer. During a subsequent doping, the arrangementcomprising laterally delimited layer sequence and spacer layer functionsas a shadowing structure and prevents doping of the region between thesource/drain regions. Since the length of the channel region dependsdirectly on the thickness of the spacer layer, an exact setting oftransistor properties which are correlated with these geometricalproperties is made possible.

In particular it should be noted that when using a deposition method(e.g. atomic layer deposition) for forming the spacer layer, thethickness thereof can be set with an accuracy of a few angstroms,whereas the accuracy of a masking technique is of the order of magnitudeof 20 nm. A significantly improved capability of setting the gate lengthis thereby realized according to the invention. The range of theunderdiffusion of dopant into the undoped channel region can becontrolled by setting the thickness of the spacer layer and theparameters during doping (type of dopant, selection and setting of theparameters of the doping method).

The deposition of a spacer is more cost-effective than the use of finemasks.

The method according to the invention avoids the use of more than twodifferent materials (p-type, n-type) for the gate regions. For anydesired thickness of a spacer layer, only one additional mask isrequired in order to produce a field effect transistor with apredetermined threshold voltage. When using a depleted, that is to sayundoped silicon layer into which the transistor is integrated,complicated implantations in the channel region (LDD regions, pocketdoping, retrograde well) are dispensable.

Preferred developments of the invention emerge from the dependentclaims.

The predetermined transistor property may be the length of the channelregion between the two source/drain regions, the threshold voltage, theleakage current characteristic, the maximum current or a transistorcharacteristic curve. According to the invention, the transistorproperty may be set by setting the dopant concentration profile or bysetting the thickness of the spacer layer.

The thickness of the spacer layer may be set by forming the spacer layerusing a chemical vapor deposition method (CVD method) or an atomic layerdeposition method (ALD method). In the case of the ALD method, inparticular, it is possible to precisely set a thickness of a layer to bedeposited down to an accuracy of one atomic layer, that is to say downto an accuracy of a few angstroms. The high accuracy when setting thethickness of the spacer layer effects a high accuracy when setting thetransistor property.

The two source/drain regions are preferably formed using an ionimplantation method or a diffusion method, the dopant concentrationprofile being set by selecting the type, the concentration and/or thediffusion properties of the dopants.

An undoped substrate is preferably used, thereby avoiding the problemsarising in conventional CMOS technologies on account of a statisticallyfluctuating dopant concentration. A complicated doping method is alsoavoided. A substrate may also be regarded as (essentially) undoped whenit has a dopant concentration that is considerably lower than a dopantconcentration of typically 10¹⁹ cm⁻³ used in the conventional CMOStechnology.

The transistor properties of the SOI field effect transistor mayalternatively be set by selecting the material of the gate region, thedopant concentration of the substrate and/or the dopant profile of thesubstrate. As a result, further parameters are available by means ofwhich the transistor properties can be set.

In particular, the dopant profile of the substrate may be set using apocket doping and/or retrograde well.

Furthermore, a second SOI field effect transistor may be formed inaccordance with the method according to the invention for producing theSOI field effect transistor on and/or in the substrate, the transistorproperties of the second SOI field effect transistor being setdifferently from those of the SOI field effect transistor. Such a needmay arise e.g. in a semiconductor memory, since the requirements made oftransistors in the logic region of a memory and in the memory region ofa memory differ greatly.

The different transistor properties of the SOI field effect transistorand of the second SOI field effect transistor preferably result solelyfrom a different thickness of the spacer layer. In other words, inparticular the same gate material may be used for the transistors withdifferent transistor properties, which results in a considerablysimplified processing.

Furthermore, a third SOI field effect transistor can be formed inaccordance with the method for producing the SOI field effect transistorin and/or on the substrate, the transistor properties of the third SOIfield effect transistor being set analogously to those of the SOI fieldeffect transistor. The conduction types of the SOI field effecttransistor and the third SOI field effect transistor are complementaryto one another. In other words, both a p-MOS transistor and an n-MOStransistor may be formed according to the invention. This takes accountof the requirements of silicon microelectronics to have transistors ofboth conduction types on an integrated circuit.

The gate regions of the SOI field effect transistor and of the secondSOI field effect transistor or of the SOI field effect transistor, ofthe second SOI field effect transistor and of the third SOI field effecttransistor may be produced from the same material. This simplifies theprocess implementation and reduces the costs.

The material of the gate regions preferably has a value of the workfunction which is essentially equal to the arithmetic mean of the valuesof the work function of heavily p-doped polysilicon (p⁺-typepolysilicon) and heavily n-doped polysilicon (n⁺-type polysilicon). Thisis referred to as a so-called “mid-gap”gate. n⁺-polysilicon has a workfunction of approximately 4.15 eV (electron volts), and p⁺-typepolysilicon has a work function of approximately 5.27 eV. Therefore, agate material with a band gap between the two values mentioned issuitable both for an n-type field effect transistor and for a p-typefield effect transistor, for example tungsten, tantalum, titaniumnitride or p⁺-doped germanium.

The material of the gate region furthermore preferably has a workfunction of between 4.45 eV and 4.95 eV.

Preferably, the transistor properties of the SOI field effect transistorand of the second SOI field effect transistor are set in such a way thatone of the two SOI field effect transistors is optimized for a lowleakage current and the other for a low threshold voltage. Thisadvantageously enables a transistor in a clock circuit to be optimizedfor a high switching speed and therefore for a low threshold voltage. Bycontrast, a transistor in a memory region may be set up in a simplemanner such that it permanently maintains a stored item of informationand therefore has a lower leakage current.

Furthermore, in accordance with the method according to the invention,at least one SOI field effect transistor may be formed as a verticaltransistor, as a transistor having at least two gate terminals (doublegate transistor) or as a fin-FET (fin field effect transistor). Theprinciple according to the invention can fundamentally be applied to alltypes of transistors.

Furthermore, in accordance with the method according to the invention,the second SOI field effect transistor may be protected from dopingduring the formation of the source/drain regions of the SOI field effecttransistor by means of a protective layer. Alternatively orsupplementary, the SOI field effect transistor may be protected fromdoping during the formation of the source/drain regions of the secondSOI field effect transistor by means of a protective layer.

At least one of the SOI field effect transistors may have at least oneadditional spacer layer on the spacer layer. In other words, it ispossible to form a plurality of spacer layers one on top of the other,the properties of the associated transistor essentially being defined bythe total thickness of the plurality of spacer layers formed one on topof the other.

The method according to the invention can be applied both to lateralthin-film SOI transistors with one gate terminal and to-double gateMOSFETS, planar transistors, vertical transistors or transistors of thefin-FET type.

Furthermore, the method can be applied without any problems to atechnology with different thicknesses of gate-insulating layers. In thiscase, the diversity of components is extended by transistors withgate-insulating layers of different thicknesses (thickness t_(ox))(so-called multi-V_(DD)/V_(T)/t_(ox) technology).

According to the invention, the thickness of the spacer layer is variedin the case of a predetermined source/drain doping (it is possible topredetermine the doping method, the dopant concentration, the dopant,etc.) and a fixed metallurgical length of the gate region. Assuming asource/drain doping profile with a spatial decrease ΔN/Δy in the dopantconcentration N as a function of the doping location y of 5 nm perdecade (logarithmic), then the effective length of the channel region,which, in the SOI field effect transistor with an undoped siliconsubstrate, depends on the length of the undoped silicon region, can beset by setting the length of the source/drain doping tails. In the caseof a thin spacer layer, the source/drain doping tails projectcorrespondingly far into the channel region, thereby shortening theeffective channel length. This results in different electricalproperties of the transistors, since the subthreshold voltage and alsoother short channel effects, such as the gate induced drain leakage(GIDL) that dominates the leakage current (off current), are influenced.Therefore, with the metallurgical gate length unchanged, a transistorhaving a thicker spacer has a higher threshold voltage and a lowerleakage current (off current) and a lower maximum current (on current)than a transistor having a thinner spacer.

An essential idea of the invention consists in the simplified settingand optimization of transistor parameters by precisely defining alateral spacer layer with respect to the gate region independently ofthe quality of an optical mask. The setting of the doping propertiesalso has a crucial influence on the threshold voltage.

It should be noted that refinements of the method for forming an SOIfield effect transistor with predeterminable transistor properties alsoapply to the SOI field effect transistor according to the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are illustrated in the figuresand are explained in more detail below.

FIG. 1A shows one field effect transistor in accordance with the priorart whose transistor properties are defined by setting a mask;

FIG. 1B shows another field effect transistor in accordance with theprior art whose transistor properties are defined by setting a mask;

FIG. 2A shows a schematic view showing the relationship between gatelength; channel length, thickness of a spacer layer and dopant profileof a field effect transistor for a low-power application;

FIG. 2B shows a schematic view showing the relationship between gatelength, channel length, thickness of a spacer layer and dopant profileof a field effect transistor for a high-performance application;

FIG. 3A shows a diagram showing input characteristic curves of a fieldeffect transistor for low-power applications;

FIG. 3B shows a diagram showing output characteristic curves of a fieldeffect transistor for low-power applications;

FIG. 4A shows a diagram showing input characteristic curves of a fieldeffect transistor for high-performance applications;

FIG. 4B shows a diagram showing output characteristic curves of atransistor for high-performance applications;

FIGS. 5A to 5D show layer sequences at different points in time during amethod for producing an SOI field effect transistor with predeterminabletransistor properties in accordance with a first exemplary embodiment ofthe invention;

FIGS. 6A to 6D show layer sequences at different points in time during amethod for producing an SOI field effect transistor with predeterminabletransistor properties in accordance with a second exemplary embodimentof the invention;

FIG. 7 shows a layer sequence in accordance with an alternative to theformation of spacer layers in accordance with the invention;

FIG. 8A shows a double gate field effect transistor;

FIG. 8B shows a fin field effect transistor; and

FIG. 8C shows a vertical field effect transistor.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

Components that are contained identically in different exemplaryembodiments are provided with the same reference numerals below.

A description is given below, referring to FIGS. 2A and 2B, of therelationship between the length of the channel region of a field effecttransistor, the length of the gate region or of the gate-insulatinglayer, the thickness of a spacer layer and also the dopant concentrationprofile.

FIG. 2A, shows, for a field effect transistor for low-power applications(large threshold voltage, small leakage current), an arrangement oflayer components along the horizontal axis, whereas the spatialdependence of the dopant concentration is shown along the vertical axisin a logarithmic representation. It is assumed that, in a surface regionof a silicon layer into which the source/drain regions of the fieldeffect transistor are implanted, the dopant concentration fallsexponentially proceeding from the outer side of the spacer layer intothe channel region. In this case, it is assumed that, from the outsideinward, the dopant concentration decreases continuously by a power often at intervals of 5 nm in each case. Under this premise, a spacerlayer having a thickness of 25 nm is required to produce a fall in thedopant concentration of the source/drain region from 10²¹ cm⁻³ to aconcentration of 10¹⁶ cm⁻³ (this corresponds to an approximately undopedsubstrate).

FIG. 2A shows the spacer layers 201, 202 at the left-hand and right-handside edge, respectively, of the gate region 203. The two spacer layers201, 202 have a thickness of 25 nm in each case. The gate region has awidth G=100 nm in the topmost illustration of FIG. 2A. Owing to the setspatial dependence of the dopant concentration, the length of thechannel region L=100 nm is equal to the length of the gate region G=100nm. The first source/drain region 204 and the second source/drain region205 are in each case formed from those regions of the silicon layer 206which lie below the associated spacer layer 201, 202, and also by theregion having a high dopant concentration that is respectively arrangedon the left and right thereof.

As shown in FIG. 2A, the first source/drain region 204 and the secondsource/drain region 205 in each case have two partial sections. In thiscase, the respective outer section corresponds to a region of thesubstrate 206 which is free of a covering with one of the spacer layers201 and 202, respectively, and has an essentially homogeneous dopantconcentration. By contrast, the first and second source/drain partialregion covered by one of the spacer layers 201 and 202, respectively,has a highly spatially dependent (exponentially spatially dependent inaccordance with the schematic illustration of FIG. 2A) dopantconcentration.

As shown in the diagrams 210, 220, 230, 240, a smaller length of thechannel region L can also be achieved by selecting a correspondinglysmaller length of the gate region G. However, the length of the channelregion L is also dependent on the thickness of the spacer layers 201,202 and also on the spatial decrease in the dopant concentration (hereby one decade every 5 nm). Therefore, a low-power field effecttransistor with a desired length of the channel region and acorrespondingly high value of the threshold voltage can be formed inparticular by selecting the dopant concentration and also the thicknessof the spacer layers 201, 202. In other words, with a spacer layerhaving a thickness of 25 nm, in the case of a fall in the dopantconcentration of 5 nm per decade, it is possible to achieve a fieldeffect transistor for low-power applications in which the length of thegate region corresponds to the length of the channel region.

By contrast, in the case of the transistor for high-performanceapplications that is shown schematically in FIG. 2B, it is advantageousthat the length of the channel region is short enough to achieve a smallthreshold voltage and therefore a short switching time. The thicknessesof the spacer layers 201, 202 are chosen in each case with a thicknessof 10 nm in the diagrams 250, 260, 270, 280 from FIG. 2B. The sameassumption as in FIG. 2A is made for the fall in the dopantconcentration. As shown for example in diagram 250, on account of theunderdiffusion at both edge regions of the gate region 203, the resultis a region having a thickness of 15 nm below the gate region, in whicha dopant concentration of more than 10¹⁶ cm⁻³ is present. Therefore, inthe cases of the diagrams 250, 260, 270, 280, the length of the channelregion L is reduced by 2*15 nm=30 nm compared with the length of thegate region L. Therefore, given a predetermined length of the gateregion, the length of the channel region can be set by choosing thewidth of the spacer layers 201, 202.

FIGS. 2A and 2B reveal, in particular, that the underdiffusion has anincreasingly great effect on the transistor properties as gate lengths Gdecrease, so that a very sensitive possibility for influencingtransistor properties is afforded particularly in future technologygenerations.

A description is given below, referring to FIG. 3A FIG. 3B, ofcharacteristic curves of a field effect transistor for low-powerapplications with a gate length of 100 nm and a channel length of 100nm. This corresponds to a configuration such as corresponds to thediagram 200 from FIG. 2A.

In diagram 300 from FIG. 3A, the electrical voltage between gate regionand source region (first source/drain region) in volts is plotted alongthe abscissa 301. The electric current I_(D) in amperes at the drainregion (second source/drain region) is plotted in a logarithmicrepresentation along the ordinate 302. FIG. 3A depicts a first curve303, corresponding to a voltage V_(DS) between the two source/drainregions of 1.2 V. Furthermore, the curve 304 corresponds to a voltageV_(DS)=0.6 V. It should be noted that both curves 303, 304 depicted aremerely by way of example; it is possible to apply any other voltagebetween the source/drain regions. The curves depicted in FIG. 3A arereferred to as input characteristic curves of the field effecttransistor.

The third and fourth curves 313, 314 depicted in the diagram 310 fromFIG. 3B are output characteristic curves of the field effect transistorfor low-power applications with a gate length of 100 nm and a channellength of 100 nm. The electrical voltage between the two source/drainregions V_(DS) in volts is plotted along the abscissa 311, whereas theelectric current at one of the source/drain regions (drain region) I_(D)in amperes is plotted along the ordinate 312 in FIG. 3B. The third curve313 corresponds to a voltage between the first source/drain region(source region) and the gate region V_(GS) of 1.2 V. By contrast, thefourth curve 314 corresponds to a voltage V_(GS)=0.6 V.

A description is given below, referring to FIG. 4A, of inputcharacteristic curves and, referring to FIG. 4B, of outputcharacteristic curves of a field effect transistor for high-performanceapplications with a gate length of 100 nm and a channel length of 70 nm.

Transistor characteristic curves for different electrical voltagesbetween the two source/drain regions V_(DS) are plotted in the diagram400 from FIG. 4A. The voltage between the source region (firstsource/drain region) and the gate region in volts is plotted along theabscissa 401, whereas the electric current at one of the twosource/drain regions (drain region) I_(D) in amperes is plottedlogarithmically along the ordinate 402 of the diagram 400. A first curve403 corresponds to a voltage between the two source/drain regionsV_(DS)=1.0 V, whereas a second curve 404 corresponds to a voltageV_(DS)=0.3 V.

Output characteristic curves of the field effect transistor from FIG. 4Aare plotted in FIG. 4B. The voltage between the two source/drain regionsV_(DS) in volts is plotted along the abscissa 411 of the diagram 410,whereas the current at one of the two source/drain regions I_(D) inamperes is plotted along the ordinate 412. A third curve 413 shows acharacteristic curve corresponding to a voltage between the gate regionand the first source/drain region (source region) V_(GS)=0.1 V, whereasthe fourth curve 414 corresponds to a voltage V_(GS)=0.3 V.

As shown by a comparison between FIG. 3A and FIG. 4A, and between FIG.3B and FIG. 4B, the transistor characteristic curves can be setsensitively as transistor properties by applying spacer layers ofdifferent thicknesses. The input and output characteristic curves shownfor the transistor with a gate length of 100 nm firstly as a low-powervariant with a channel length of 100 nm (spacer having a thickness of 25nm) and secondly as a high-performance variant with a channel length of70 nm (spacer having a thickness of 10 nm) exhibits distinctdifferences. All other parameters of these transistors are identical.

The dopant concentration of the silicon layer 206 is in each case 10¹⁶cm⁻³, the thickness of the gate-insulating layer is 2 nm (silicondioxide), the vertical thickness of the silicon layer 206 is 10 nm andthe gate material is p⁺-doped germanium.

A description is given below, referring to FIG. 5A to FIG. 5D, of amethod for producing an SOI field effect transistor with predeterminabletransistor properties in accordance with a first exemplary embodiment ofthe invention. FIG. 5A to FIG. 5D in each case show a field effecttransistor for high-performance requirements with a low thresholdvoltage and high leakage current on the left-hand side and a transistorfor low-power applications with a high threshold voltage and low leakagecurrent on the right-hand side.

FIG. 5A shows layer sequences 500, 510 corresponding to a partlyproduced transistor in SOI technology. The layer sequences 500, 510 areprocessed on the same SOI substrate 501 comprising a silicon substrate502, a silicon dioxide layer 503 and a silicon layer 504. A firstlaterally delimited layer sequence shown in the left-hand half of FIG.5A is constructed from a first gate-insulating layer 505 and from afirst gate region 506. Furthermore, a first TEOS protective layer 507(tetraethyl orthosilicate) is applied on the sidewalls of the firstlaterally delimited layer sequence. The protective layer serves forelectrically and mechanically decoupling the first laterally delimitedlayer sequence from the surroundings. A second laterally delimited layersequence shown in the right-hand half of FIG. 5A is constructed from asecond gate-insulating layer 511, a second gate region 512 and a secondTEOS protective layer 513.

In order to obtain the layer sequences 520, 530 shown in FIG. 5B, theright-hand region in accordance with FIG. 5B is covered with aphotoresist layer 531 in order subsequently to enable processingexclusively of the layer sequence shown on the left in FIG. 5B. In afurther method step, doping atoms of the n conduction type are implantedinto two surface regions of the silicon layer 504 using an ionimplantation method in order to obtain two source/drain regions 521, 522of the transistor with a low threshold voltage shown in the left-handhalf of FIG. 5B. On account of the covering with photoresist 531,implantation ions are protected from penetrating into that surfaceregion of the SOI substrate 501 which is illustrated in the right-handhalf of FIG. 5B.

In order to obtain the layer sequences 540 and 550 shown in FIG. 5C,firstly the photoresist 531 is removed using a suitable etching method.In a further step, a spacer layer 541 and 551 having a predeterminedthickness is in each case formed on the sidewalls of the first andsecond laterally delimited layer sequences, respectively, which iseffected using the ALD method (atomic layer deposition). The ALD methodmakes it possible to predetermine the thickness of the spacer layer “d”down to an accuracy of one atomic layer, that is to say down to a fewangstroms.

In order to obtain the layer sequences 560, 570 shown in FIG. 5D,firstly a further photoresist layer 561 is deposited on the layersequence 540 in order to shield the associated surface region of the SOIsubstrate from further processing. Afterward, in that surface region ofthe SOI layer sequence 501 which is free of the further photoresistlayer 561, a third and a fourth source/drain region 571, 572 with apredetermined dopant concentration profile are formed by introducingdopant atoms of the n conduction type into two surface regions of thesilicon layer 504 near the sidewalls of the second spacer layer 551. Thesecond laterally delimited layer sequence and the second spacer layer551 are set up in such a way that they form a shading structure forpreventing the dopant of the n conduction type from being introducedinto surface regions of the silicon layer 504 between the third andfourth source/drain regions 571, 572. The transistor properties of theSOI field effect transistor shown in the right-hand region of FIG. 5Dare defined by setting the thickness “d” of the second spacer layer 551and by setting the dopant concentration profile during the formation ofthe third and fourth source/drain regions 571, 572. The ion implantationmethod is used as a method for implanting the dopant atoms in the thirdand fourth source/drain regions 571, 572. The dopant concentrationprofile of the third and fourth source/drain regions 571, 572 can bepredetermined by setting the dopant atom type, the energy of the dopingatoms and also further method parameters.

The SOI field effect transistor in the left-hand partial region of FIG.5D has a channel region with a shorter length than the SOI field effecttransistor shown in the right-hand partial region of FIG. 5D. The lengthof the channel region of the left-hand SOI field effect transistor isapproximately 2 d less than in the case of the right-hand SOI fieldeffect transistor since the additionally applied second spacer layer 551serves as a shading structure during the introduction of dopant atomsinto the right-hand field effect transistor in accordance with FIG. 5D.

Furthermore, it should be noted that the first TEOS protective layer 507and the second TEOS protective layer 513 have a thickness ofapproximately 10 nm in order to enable a sufficiently good insulationeffect for the layer stack comprising gate-insulating layer and gateregion. By contrast, the thickness “d” of the second spacer layer 551 isset in such a way that the right-hand SOI field effect transistor isformed as a low-power field effect transistor. The functionalities ofthe TEOS protective layers 507, 513, on the one hand, and of the spacerlayers 541, 551 are fundamentally different.

A description is given below, referring to FIG. 6A to FIG. 6D, of asecond preferred exemplary embodiment of the method according to theinvention for producing an SOI field effect transistor withpredetermined transistor properties.

The layer sequences 600, 610 shown in FIG. 6A correspond to the layersequences 500, 510 shown in FIG. 5A.

In order to obtain the layer sequences 620, 630 shown in FIG. 6B, aspacer layer 621 having the thickness “l” is deposited both on theleft-hand surface region and on the right-hand surface region of thelayer sequences in accordance with FIG. 6B. This is done by using a CVDmethod (“chemical vapor deposition”). The thickness “l” of the spacerlayer 621 is a crucial parameter for setting the length of the channelregion of the right-hand SOI field effect transistor in accordance withFIG. 6B. The spacer layer 621 is produced from silicon nitride.

In order to obtain the layer sequences 640, 650 shown in FIG. 6C, theright-hand surface region in accordance with FIG. 6C is covered with aTEOS hard mask 651 (tetraethyl orthosilicate) in order to protect thissurface region from etching in a further method step. In a furthermethod step, in the case of the left-hand surface region in accordancewith FIG. 6C, the spacer layer 621 made of silicon nitride is removedusing a wet-chemical etching method. A wet-chemical etching method of atype which is suitable for etching silicon nitride is used for thispurpose, whereas silicon dioxide (i.e. also the TEOS hard mask 651) isprotected from etching. As a result, only the spacer layer 621 from theleft-hand surface region is removed.

In order to obtain the layer sequences 660, 670 shown in FIG. 6D,firstly the TEOS layer 651 is removed using a suitable etching method.As shown in FIG. 6C, the left-hand laterally delimited layer stack isapproximately 2*l narrower than the right-hand layer stack, where l isthe thickness of the spacer layer 621. Afterward, both the left-handlayer stack and the right-hand layer stack are subjected to an ionimplantation method, thereby forming a first source/drain region 661, asecond source/drain region 662, a third source/drain region 663 and afourth source/drain region 664. The source/drain regions of theleft-hand SOI field effect transistor in accordance with FIG. 6C areformed by means of the first and second source/drain regions 661, 662,whereas the source/drain regions of the right-hand SOI field effecttransistor in accordance with FIG. 6C are formed by means of thesource/drain regions 663, 664. Owing to the functionality of the spacerlayer 621 as part of a shading structure, that distance between the twosource/drain regions by which the length of the channel region isdefined, in the case of the layer sequence 670, is approximately 2*lgreater than in the case of the layer sequence 660. Therefore, the SOIfield effect transistor 660 has a lower threshold voltage than the SOIfield effect transistor 670.

Furthermore, the SOI field effect transistor 670 has a lower leakagecurrent than the SOI field effect transistor 660.

The method described with reference to FIG. 6A to FIG. 6D has theadvantage, in particular, that a single common implantation methodsuffices for forming the source/drain regions of both SOI field effecttransistors.

Analogously to the production methods described with reference to FIG.5A to FIG. 5D and FIG. 6A to FIG. 6D, respectively, a p-channel SOIfield effect transistor and an n-channel SOI field effect transistor mayalso be produced in a CMOS process. Furthermore, a multiple applicationof the procedure is conceivable in order to produce a still widespectrum of different components, in particular SOI field effecttransistors.

After carrying out the method steps described with reference to FIG. 5Ato FIG. 5D and FIG. 6A to FIG. 6D, respectively, it is possible to carryout further process steps that are specific in particular to thethin-film SOI technology, such as the production of “elevated”source/drain regions, siliciding or the formation of a conventionalback-end region. When using a gate region made of a metallic materialinstead of a p⁺-doped polysilicon germanium gate, the latter is replacedby a metallic gate region.

FIG. 7 shows a layer sequence 700 that is similar to the layer sequence540 shown in the left-hand region of FIG. 5C.

An essential difference between the layer sequence 700 from FIG. 7 andthe layer sequence 540 from FIG. 5C is that, in the case of the layersequence 700, a spacer sidewall 701 is provided instead of the firstspacer layer 541. The spacer sidewall may be obtained for example byetching back the spacer layer 541 from FIG. 5C. The spacer sidewall 701essentially fulfills the same functionality as the spacer layer 541.

Furthermore, the production of different types of transistor (low-powertransistor, high-performance transistor) using a spacer of variablethickness that has been described with reference to FIG. 5A to FIG. 7can also be applied to other MOSFET variants. Exemplary embodimentsthereof are shown in FIG. 8A to FIG. 8C.

FIG. 8A shows a double gate transistor 800, in which a channel region801 is surrounded vertically on both sides in a controllable manner by afirst gate region 802 and by a second gate region 803. Thegate-insulating regions between the first gate region 802 and thechannel region 801, on the one hand, and between the second gate region803 and the channel region 801, on the other hand, are not shown in FIG.8A. Furthermore, the double gate transistor 800 has a first source/drainregion 804 and a second source/drain region 805. Moreover, a siliconsubstrate 806 and also a silicon dioxide layer 807 on the siliconsubstrate 806 are provided. Furthermore, a first spacer region 808 madeof silicon nitride and a second spacer region 809 made of siliconnitride are provided, by means of which the length of the channel regioncan be set according to the invention.

Furthermore, FIG. 8B shows a fin field effect transistor (fin-FET). Inaccordance with fin-FET technology, the current flow through the channelregion is controlled from two sides. A type of “forked” design of thegate region distinctly reduces leakage currents through the channelregion. FIG. 8B shows in particular a first, a second, a third and afourth spacer region 821 to 824, it being possible to set the length ofthe channel region by setting the thickness of the spacer layers 821 to824.

FIG. 8C shows a vertical field effect transistor 840 having a bulksilicon region 841. A first spacer region 842 and a second spacer region843 are formed on the first and second gate regions 802, 803,respectively, in such a way that the length of the channel region can beset thereby.

1. A first SOI field effect transistor with predetermined transistorproperties, comprising: a laterally delimited layer sequence with agate-insulating layer and a gate region on an undoped substrate; aspacer layer having a predetermined thickness on at least a portion ofthe sidewalls of the laterally delimited layer sequence; and twosource/drain regions in two surface regions of the substrate which areadjoined by the spacer layer, with a predetermined dopant concentrationprofile, the layer sequence and the spacer layer forming a shadingstructure that prevents dopant from being introduced into a surfaceregion of the substrate between the two source/drain regions during theproduction of the first SOI field effect transistor, wherein thepredetermined transistor properties of the first SOI field effecttransistor are set by setting the thickness of the spacer layer and bythe dopant concentration profile.
 2. The first SOI field effecttransistor as claimed in claim 1, wherein the length of the channelregion between the two source/drain regions, the threshold voltage, theleakage current characteristic, the maximum current, and/or a transistorcharacteristic curve is set as the predetermined transistor properties.3. The first SOI field effect transistor as claimed in claim 1, whereinthe thickness of the spacer layer is set by forming the spacer layerusing a chemical vapor deposition method or an atomic layer depositionmethod.
 4. The first SOI field effect transistor as claimed in claim 1,wherein the two source/drain regions are formed using an ionimplantation method or a diffusion method, and the dopant concentrationprofile is set by choosing the type, the concentration, and/or thediffusion properties of the dopant atoms.
 5. The first SOI field effecttransistor as claimed in claim 1, wherein the predetermined transistorproperties of the first SOI field effect transistor are set by selectingthe material of the gate region, the dopant concentration of thesubstrate, and/or the dopant profile of the substrate.
 6. The first SOIfield effect transistor as claimed in claim 5, wherein the dopantprofile of the substrate is set using a pocket doping and/or aretrograde well.
 7. The first SOI field effect transistor as claimed inclaim 1, further comprising a second SOI field effect transistor formedsimilar to the first SOI field effect transistor on and/or in thesubstrate, wherein the predetermined transistor properties of the secondSOI field effect transistor are different from those of the first SOIfield effect transistor.
 8. The first SOI field effect transistor asclaimed in claim 7, wherein the different transistor properties of thefirst SOI field effect transistor and of the second SOI field effecttransistor result solely from different thicknesses of the spacerlayers.
 9. The first SOI field effect transistor as claimed in claim 1,further comprising a third SOI field effect transistor formed similar tothe first SOI field effect transistor on and/or in the substrate,wherein the predetermined transistor properties of the third SOI fieldeffect transistor are analogous to those of the first SOI field effecttransistor, and the conduction types of the first SOI field effecttransistor and the third SOI field effect transistor are complementaryto one another.
 10. The first SOI field effect transistor as claimed inclaim 7, further comprising a third SOI field effect transistor formedsimilar to the first SOI field effect transistor on and/or in thesubstrate, wherein the predetermined transistor properties of the thirdSOI field effect transistor are analogous to those of the first SOIfield effect transistor, and the conduction types of the first SOI fieldeffect transistor and the third SOI field effect transistor arecomplementary to one another.
 11. The first SOI field effect transistoras claimed in claim 7, wherein the gate regions of the first SOI fieldeffect transistor and of the second SOI field effect transistor or ofthe first SOI field effect transistor, of the second SOI field effecttransistor, and of the third SOI field effect transistor are producedfrom the same material.
 12. The first SOI field effect transistor asclaimed in claim 11, wherein the material of the gate regions has avalue of a work function which is essentially equal to an arithmeticmean of values of a work function of heavily p-doped polysilicon andheavily n-doped polysilicon.
 13. The first SOI field effect transistoras claimed in claim 11, wherein the material of the gate regions isgermanium, tungsten, tantalum, and/or titanium nitride.
 14. The firstSOI field effect transistor as claimed in claim 12, wherein the materialof the gate region has a work function of between 4.45 electron voltsand 4.95 electron volts.
 15. The first SOI field effect transistor asclaimed in claim 7, wherein the predetermined transistor properties ofthe first SOI field effect transistor and of the second SOI field effecttransistor are such that one of the two SOI field effect transistors isoptimized for a low leakage current and the other for a low thresholdvoltage.
 16. The first SOI field effect transistor as claimed in claim1, wherein at least one SOI field effect transistor is a verticaltransistor, a transistor having at least two gate terminals, or afin-FET.
 17. The first SOI field effect transistor as claimed in claim7, further comprising a protective layer that protects the second SOIfield effect transistor from doping during a formation of thesource/drain regions of the first SOI field effect transistor, and/or aprotective layer that protects the first SOI field effect transistorfrom doping during a formation of the source/drain regions of the secondSOI field effect transistor.
 18. The first SOI field effect transistoras claimed in claim 7, wherein at least one of the SOI field effecttransistors has at least one additional spacer layer on the spacerlayer.